uWhat is
IR drop?
nVoltage drops in power (and bounces in
ground) network due to electrical parameters (resistance, capacitance,
inductance) of power (ground) network
uWhat is
the impact?
nDecreases power supply voltage across the
cells
nLeads to increased cell delay and degraded
performance
nSevere IR drop can lead to functionality
failures and reduced yield
uWhat is
the prevention?
nRobust power & ground routing
u Static
IR drop
n Average
voltage, Vavg drop across the power/ground network, based on average
power or current - i.e. Iavg * R on chip
u Dynamic
IR drop
n Time-varying
V(t) drop on power/ground network
n Dynamic
IR drop additionally models the following
–
Package inductance
–
Decoupling Capacitance
–
Dynamic current need (di/dt)
Modern designs are very sensitive to noise, due to the presence of a larger number of potential noise generators that consume the noise margins built into a design. The power grid, which provides the supply and ground signals throughout the chips, is one of the most important sources of noise.
On-chip decoupling capacitors, or “decaps”, are attached to the power and ground network to decrease noise effects. Decoupling capacitors are also an effective way to reduce or minimize peak IR drop.
Figure 2 represents an equivalent circuit representation of the power and ground network with a decoupling capacitor cell attached. The decoupling capacitor cell is essentially a low pass filter with an intrinsic resistance and capacitance. This is represented as Rdecap and Cdecap in Figure 2. Rmesh represents the resistance of the power and ground network, VDD is the voltage source and Iload represents the load current.
Knowledge of Leakage Numbers
Unlike filler cells, decoupling capacitors have high leakage current and should not be inserted into the design liberally as is done with filler cells. Knowing the decoupling capacitor leakage numbers from the library is a must before inserting these cells.
Location of the Decoupling Capacitor Cell
The location of the decoupling capacitor cell is very important in reducing the peak IR drop. The decoupling capacitor cell should be inserted in an area that is close to the peak IR drop.
There are also some possible situations where decoupling capacitor insertion might not be effective. These include the following:
•
Static causes: The power and ground network is not properly routed, causing some instances to be isolated or far away from the ideal supply. In this case, a high dynamic voltage drop is created due to a large resistance value. This scenario might require unrealistically large decoupling capacitor values to reduce the voltage drop.
•
Inductive causes: Inductive (Ldi/dt) noise is the dominant portion of dynamic voltage drop. The amount of affordable on-chip decoupling capacitor insertion might be much less than what is needed to reduce the noise effectively.
Identifying the root causes of IR drop is a must, and proper care must be taken to eliminate the IR drop contributions from sources described above.
Filler cells are inserted during the chip finishing stage in IC Compiler. Filler cells must be inserted in the design for the decoupling capacitor insertion flow described here, because the flow swaps filler cells for decoupling capacitor cells where needed. Also, the flow requires characterized libraries for the decoupling capacitor cells.
The IC Compiler decoupling capacitor analysis flow focuses on achieving the user-specified target dynamic IR voltage drop, while minimizing the decoupling capacitor insertion cost. This cost is a function of the total area and leakage of the inserted decoupling capacitors. Figure 4 illustrates the insertion flow. IC Compiler first looks at the preplaced filler cells (shown in white), and replaces them then virtually with decoupling capacitor cells (shown in blue). The available filler area is used as candidate locations for decoupling capacitor cell swapping. At each analysis step, IC Compiler removes unneeded decoupling capacitor cells to minimize the cost function of the inserted decoupling capacitors, while meeting the user-provided voltage drop reduction target. IC Compiler might perform several decoupling capacitor removal iterations during the voltage drop analysis to determine an optimal solution. When the analysis is complete, IC Compiler provides suggestions for decoupling capacitor insertion and writes out a file containing the list of filler instances that should be replaced with decoupling capacitor cells.
The required inputs needed to perform decoupling capacitor analysis in IC Compiler are listed below.
Desired or target IR drop reduction
This is the target IR drop reduction the user wishes to achieve. The default reduction is set to 10%. Use the set_rail_options –vd_threshold IC Compiler command to specify the target IR drop reduction.
Filler cell and decoupling capacitor cell masters
These are the library cell master names of the filler and decoupling capacitor cells that can be swapped. The cell footprint for the decoupling capacitor masters must match the corresponding filler cells. For example, a FILLX4 filler master must have DCAPX4 decoupling capacitor master. Use the set_rail_options -filler_lib_cells command to specify filler lib cells, and the set_rail_options –decap_lib_cells command to specify the decoupling capacitor lib cells.
PrimeRail and PTPX binaries
The analyze_rail command uses the PrimeRail and PrimeTime PX tools to perform decoupling capacitor analysis. Make sure that IC Compiler can locate these binaries. By default, IC Compiler uses the binaries defined in the default UNIX path. The set_rail_options –pr_exec_dir command and the set_rail_options -pt_exec_dir command can also be used to specify the PrimeRail and PrimeTime PX binary locations respectively.
The analyze_rail –decap { net_name } IC Compiler command performs decoupling capacitor analysis. Multiple net names are not currently supported; the analysis net has to be a single net. Also, the analysis mode must be set to dynamic to perform decoupling capacitor analysis. This is set by using the set_rail_options -analysis_mode dynamic command. You can see the sample IC Compiler decoupling capacitor analysis script in the Appendix.
During the decoupling capacitor analysis, IC Compiler writes a hidden ASCII ECO file (.file) that contains the list of the filler instances that need to be swapped with the corresponding decoupling capacitor cell masters. IC Compiler writes this ECO file once per analysis iteration. By default, IC Compiler writes the ECO file and log file (analyze_rail.log*) to pr_<current_design> or to the directory specified by using the set_rail_options –output_dir command. A sample log file illustrating this iteration process is shown in Figure 5. This log file includes IR drop, capacitance numbers, leakage, and other analysis results from the initial decoupling capacitor insertion, and from each iteration of decoupling capacitor removal as the analysis converges toward the target voltage drop.
Figure 5 Decoupling capacitor analysis results from log file
finish VDD
DECAP: [ITERATION 0] [VOLTAGE DROP 1.17519 mV (91.5%)] [TOTAL CAP 1942.81 nF] [FILLER CAP 1942.75 nF] [DECAP LEAKAGE 2537.21 nA]
DECAP: ude file .decap_ude_0 is created.
DECAP: [ITERATION 1] [VOLTAGE DROP 6.72546 mV (51.5%)] [TOTAL CAP 71.3119 nF] [FILLER CAP 71.2954 nF] [DECAP LEAKAGE 101.624 nA]
DECAP: ude file .decap_ude_1 is created.
DECAP: [ITERATION 2] [VOLTAGE DROP 6.74446 mV (51.3%)] [TOTAL CAP 30.7109 nF] [FILLER CAP 30.6944 nF] [DECAP LEAKAGE 34.2418 nA]
The example in Figure 6 lists the contents of the ECO file. The .decap_ude_2 file is the hidden ECO (.file) that was created by IC Compiler.
Figure 6 ECO file contents
unix_shell> cat pr_decap/.decap_ude_2
replace_cell_reference [get_cells -all \ xofiller_FILL8LVT_707 ] -lib_cell DCAP8LVT ;# FILL8LVT
replace_cell_reference [get_cells –all \ xofiller_FILL16LVT_427 ] -lib_cell DCAP16LVT ;# FILL16LVT
replace_cell_reference [get_cells –all \ xofiller_FILL32LVT_575 ] -lib_cell DCAP32LVT ;# FILL32LVT
replace_cell_reference [get_cells –all \ xofiller_FILL64LVT_1684 ] -lib_cell DCAP64LVT ;# FILL64LVT
The file contains the replace_cell_reference IC Compiler command which replaces various instances from a filler master to a decoupling capacitor master.
After generating the ECO file, decoupling capacitor insertion can be performed by sourcing the ECO file in IC Compiler. Select the ECO file corresponding to the iteration that best fits the IR drop target and leakage numbers.
icc_shell > source -echo pr_decap/.decap_ude_2
icc_shell > source -echo pr_decap/.decap_ude_2
replace_cell_reference [get_cells -all \ xofiller_FILL8LVT_707 ] -lib_cell DCAP8LVT ;# FILL8LVT
1
replace_cell_reference [get_cells –all \ xofiller_FILL16LVT_427 ] -lib_cell DCAP16LVT ;# FILL16LVT
1
replace_cell_reference [get_cells –all \ xofiller_FILL32LVT_575 ] -lib_cell DCAP32LVT ;# FILL32LVT
1
replace_cell_reference [get_cells –all \ xofiller_FILL64LVT_1684 ] -lib_cell DCAP64LVT ;# FILL64LVT
1
This script replaces the filler cells in the ECO file with decoupling capacitor cells.
Sample IC Compiler decoupling capacitor ECO script
source scripts/icc_setup.tcl
## OPEN DESIGN
##############
open_mw_lib ChipTop_LIB
open_mw_cel decap
link
## SET RAIL ANALYSIS OPTIONS
############################
set_rail_options -use_pins_as_pads true \
-output_dir pr_decap \
-switching_activity {vcd results/sim_iccg.vcd tb/ChipTop} \
-filler_lib_cells "FILL4LVT FILL8LVT FILL16LVT FILL32LVT FILL64LVT" \
-decap_lib_cells "DCAP4LVT DCAP8LVT DCAP16LVT DCAP32LVT DCAP64LVT" \
-analysis_mode dynamic
report_rail_options
## DECAP ANALYSIS
##################
## ANALYZE VDD RAIL
analyze_rail -decap {VDD}
## INSERT DECAP CELLS
######################
source -echo pr_decap/.decap
